/*
 * Copyright : (C) 2022 Phytium Information Technology, Inc.
 * All Rights Reserved.
 *
 * This program is OPEN SOURCE software: you can redistribute it and/or modify it
 * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
 * either version 1.0 of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
 * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the Phytium Public License for more details.
 *
 *
 * FilePath: crt0.S
 * Date: 2022-02-10 14:53:41
 * LastEditTime: 2022-02-17 17:28:18
 * Description:  This file is for 32bit C run-time code
 *
 * Modify History:
 *  Ver   Who        Date         Changes
 * ----- ------     --------    --------------------------------------
 *  1.0  huanghe   2021-11       initialization
 *  1.1  zhugengyu 2022/06/05    add debugging information
 */

.set FPEXC_EN, 0x40000000       /* FPU enable bit, (1 << 30) */

    .text
    .align 2

.LbssStart:
    .long _sbss

.LbssEnd:
    .long _ebss


.LdataStart:
    .long _sdata

.LdataEnd:
    .long _edata

.LRomEnd:
    .long _sidata

    .globl _startup
_startup:
    mov r0, #0

.LbssClearPrepare:
    /* clear bss */
    ldr r1, .LbssStart      /* calculate beginning of the BSS */
    ldr r2, .LbssEnd        /* calculate end of the BSS */

.LbssClearLoop:
    cmp r1,r2
#ifndef LOSCFG_AMP_REMOTE
    bge .LdataCopyPrepare   /* If no BSS, no clearing required */
#else
    bge .LdataCopyFinish    /* If no BSS, no clearing required */
#endif
    str r0, [r1], #4
    b   .LbssClearLoop

#ifndef LOSCFG_AMP_REMOTE
.LdataCopyPrepare:
    /* copy data */
    ldr r0, .LRomEnd
    ldr r1, .LdataStart
    ldr r2, .LdataEnd

.LdataCopyLoop:
    cmp r1,r2
    ldrlt r3, [r0], #4      /* t load 4 bytes of data from ROM into R3 */
    strlt r3, [r1], #4
    blt .LdataCopyLoop
#endif

.LdataCopyFinish:
    /* 启用对FP寄存器的访问. */
    mov r1, #0xfffffff
    mcr p15, 0, r1, c1, c0, 2 /* CPACR full access to cp11 and cp10. */

    /* 启用MMU和缓存 */
    bl InitMMUTable
    bl InitCache

    /* 启用VFP */
    vmrs r1, FPEXC          /* read the exception register */
    orr r1,r1, #FPEXC_EN    /* set VFP enable bit, leave the others in orig state */
    vmsr FPEXC, r1          /* write back the exception register */

    bl FTraceCEntry

    cpsie i                 /* 使能中断 */

    /* make sure argc and argv are valid */
    mov r0, #0
    mov r1, #0

    bl main

.Lexit: /* should never get here */
    b .Lexit
